3 Ghz counter and power detector build Part III Cpld

The counter not only has a Dsp that needs programming, there is also a Cpld.
Cplds (Complex Programmable Logical Devices ) are very interesting parts.
A Cpld gives you the possibility to create your own integrated circuit.
In a very simplified explanation I would say they are made of thousands of gate arrays and configurable wires which connect between the gates and the pins.
Programming a Cpld is more like routing a pcb than programming a microcontroller.
A common language to describe your circuit is VHDL (Verilog Hardware Definition Language).

Cplds and Fpga (Field Programmable Gate Array) are very powerfull devices.
They can process tasks massively parallel are very fast but also expensive and tricky to program.

Programming a Cpld is usually done via Jtag interface.
I downloaded the Altera programmer and used a 5$ Jtag programmer clone of the Altera Usb Blaster.

Everything worked immediately .
The last step of the counter build is to add the rest of the passive components.

Successful programming of the Cpld

Links:
3 Ghz counter and power detector build Part I
3 Ghz counter and power detector build Part II
Elektor project page
Altera Homepage

3 Ghz counter and power detector build Part II Troubles programming the Dsp

When I populate a new pcb I first solder the chips with the smallest footprints.
Next in order are the bigger ics and power supply chips.

Then I make a break and program the controller.
To program a Pic chip you just need the chip, some decoupling capacitors a pullup resistor  on the reset line and the three programming data lines MCLEAR (reset line),PGC,PGD.
Usually pic chips are super easy to program, compared to the Atmel Avr line they even don't need an oscillator.

So with high hopes I started  the Microchip ide Mplab, connected the programmer to the board (using pogo pins to avoid solderin a connector) and clicked the connect menu entry.


Connecting to MPLAB ICD 2
...Connected
Setting Vdd source to target
ICDWarn0020: Invalid target device id (expected=0xF0F, read=0x0)
...Reading ICD Product ID
Running ICD Self Test
... Failed Self Test.  See ICD2 Settings (Programmer->Settings) (status tab) for details.
MPLAB ICD 2 ready for next operation

Hmmmm
At least one head scratching hours later, no difference.
The Dsp chip simply told me in this working environment we ar on strike, go f*** yourself.
Now what to do if a processor is in working refusal ?
The best way is to negotiating with their local labour union boss, the datasheet.
In a good datasheet there is often a minimal working environment section and voila there is a strange pin number 7 called Vcap/Vdcore.

Hmmmm

After further reading I understood the internal core runs on 2.5V and to avoid an extra power line the chi provides an internal regulator which needs a decoupling capacitor.

Next try:

Connecting to MPLAB ICD 2
...Connected
Setting Vdd source to target
Target Device dsPIC33FJ32GP204 found, revision = Rev 0x3006
...Reading ICD Product ID
Running ICD Self Test
...Passed
MPLAB ICD 2 ready for next operation
Programming Target...
...Validating configuration fields
ICDWarn0046:  Because clock switching is enabled, MPLAB ICD 2 requires the user to cycle target power after a program operation.
...Erasing Part
...Programming Program Memory (0x0 - 0x54FF)
Verifying...
...Program Memory
...Verify Succeeded
...Programming Configuration Bits
.. Config Memory
Verifying configuration memory...
...Programming succeeded

BOOOOOM
Success, the chip is now programmed.
Now that was some heavy lifting , usually troubles appear from the most unexpected direction.

Time for some pictures:

Dsp processor

PLL chip very small footprint

 Log Power measurement , Cpld and Pll chips

Links:
3 Ghz counter and power detector build Part I
Elektor project page

3 Ghz counter and power detector build

To measure the output of the phase locked oscillators for the spectrum analyzer I needed a fairly accurate frequency counter.

I test a counter usually against my 10 Mhz rubidium source.
Neither a cheap 1 Ghz counter from China nor a self built counter built around pic micro controller produced good results. They were way of,...

This new project which I found on the Elektor homepage raised my curiosity.
Usually I don't like Eektor projects that much,  they tend to use the most expensive components but then deliver a mediocre circuit that does not make use of all the bells and whistles this components could deliver. On the other hand I like the magazine and always  hope this time they hit gold.

First for pre scaling (dividing the input signal down) it uses a cheap pll chip instead of an expensive dedicated pre scaler. (nice!)
Second as counter it uses a CPLD device and provides the VHDL (Verilog hardware description language) sources.
Third it uses a 0.5 ppm crystal oscillator as reference.
Forth it can measure the power level but unfortunately only within an accuracy of 4 db (if the frequency is modulated). I can live with that, power meters almost always have trouble with modulated sigbak sources .

I ordered an empty pcb, luckily I already ad most of the needed parts in my lab.
In the build process I first populated the most difficult parts like the qfn power detector, the input amplifier and than the rest of the integrated circuits.
Then I soldered the passive components.
Afterwards the big components like the display were soldered.

Before power up I checked for short circuits.

Next step is programming the Cpld and the Dsp about which I will tell you in another blog post.

Counter function blocks

             1) Hf input
             2) Dc input
             3) Battery input
             4) Input splitter (Log detector, Counter)
             5) Log Detctor
             6) Preamp
             7) Pll (prescaler)
             8) Oscillator
             9,10) Linear regulators
             11) Reference
             12) Polyfuse circuit protection
             13) Jtag disable
             14) Jtag (Busblaster programmer input)
             15) Icd (Dsp programmer input)
             16) Cpld
             17) Dsp

Links:
Project link